The present invention relates generally to phase-locked loops, and more specifically to linear full-rate phase detectors and clock and data recovery circuits.
Data networking has exploded over the last several years, and has changed the way people work, get information, and spend leisure time. Local Area Networks (LANs) in the workplace allow for centralized database and file sharing and archiving. Wireless Application Protocol (WAP) enabled mobile phones operating over a Wide Area Network (WAN) allow users to access news updates and stock quotes. The Internet has transformed shopping and research, and has spawned a new recreational activity—Web surfing. Many computers are used primarily as interfaces to these networks, thus the expression “the network is the computer” has become popularized.
Devices such as Network Interface Cards (NICs), bridges, routers, switches, and hubs move data between users, between users and servers, or between servers. Data moves over a variety of media such as fiber optic or twisted pair cables, and the air. These media are similar in that they distort data, making it difficult to be read by a receiving device. Light-waves in a fiber optic cable travel not only down the cable's core, but bounce off the core-cladding interface, and thus tend to disperse. Twisted pair cables have filtering properties that tend to attenuate higher frequencies. This limited bandwidth also creates interference between individual data bits, known as Inter-Symbol Interference (ISI). Wireless signals tend to bounce off buildings and other surfaces in a phenomenon known as multipath, which results in the smudging of one data bit into the next.
Therefore, each of these devices, NICs, bridges, routers, switches, and hubs, receive distorted data and must “clean it up”, or retime it, for use either by the device itself, a device attached to it, or for re-transmission. A useful building block for this is the phase-locked loop (PLL). PLLs accept distorted data, and provide a CLOCK signal and retimed (or recovered) data as outputs.
But the task for PLLs has lately begun to be a lot tougher. Equipment operating at data rates of one Gigabit per second is replacing 100 Megabit devices, which recently replaced 10 Megabit units. Exacerbating this problem is the competitive nature of the networking business itself. Pricing pressures are enormous, and using high speed, specialized processes raises system costs. Thus, the goal is to create integrated circuits that are capable of operating at these data rates, but which can be made using relatively inexpensive process technologies. What is needed are PLLs which can be made inexpensively, while still operating at these high frequencies.